1. Field of the Invention
The present invention relates to a signal processor for amplifying picture signals provided by an image sensor, and sampling and holding the amplified picture signals.
2. Description of the Related Art
Referring to FIG. 6 showing a picture signal processor for reading, in a time series, a plurality of picture signals produced by an image sensor, there are shown an image sensor 30, dual correlation sampling circuits 31A to 31M, sample-and-hold circuits 32A to 32M, switches 33A to 33M, a buffer 34, an output terminal 35, and signal processing channels A to M respectively for picture signals.
An input bias voltage of an input parasitic capacitance, not shown, or the like is applied to the dual correlation sampling circuits 31A to 31M before applying picture signals provided by the image sensor 30. When a picture signal is superposed on the input bias voltage, the dual correlation sampling circuits 31A to 31M amplify only the picture signal and provides an amplified picture signal. The sample-and-hold circuits 32A to 32M holds the outputs of the dual correlation sampling circuits 31A to 31M, respectively.
Since the respective operations of the signal processing channels A to M are similar to each other, the operation of the signal processing channel A will be described by way of example. The dual correlation sampling circuit 31A amplifies a picture signal (input signal) produced by one of the picture reading elements of the image sensor 30, and the sample hold circuit 32A holds the amplified picture signal provided by the dual correlation sampling circuit 31A. Thus, the sample-and-hold circuits 32A to 32M of the signal processing channels A to M holds the amplified picture signals obtained by amplifying the output picture signals of the picture reading elements of the image sensor 30. The switches 33A to 33M are closed sequentially to send out the amplified picture signals through the buffer 34 to the output terminal 35, so that a time series of the amplified picture signals is obtained.
It is desired that the amplified picture signals of the time series are provided continuously with the shortest possible idle period. If there is an idle period between the successive amplified picture signals, the dual correlation sampling circuits 31A to 31M must be controlled so as not to read the next data, which requires a complex control operation, and clock frequency must be increased during an output period, requiring the widening of the frequency band of the buffer.
When sending out the data continuously, problems arise in the sample-and-hold circuits. The sample-and-hold circuit is unable to hold the next data while the same is sending out the previously held data. Therefore, when one control signal is used to control the sample holding operations of the signal processing channels, the output operation must be interrupted during the sampling operation. A technique proposed to avoid the interruption of the output operation during the sampling operation duplicates the sample-and-hold circuit of each signal processing channel. A dual correlation sampling circuit and a sample-and-hold circuit will be described hereinafter.
[Double Correlation Sampling Circuit] PA0 (1) Application of Input Bias Voltage PA0 (2) Application of Input Bias Voltage and Input Signal PA0 (1) Period t.sub.1 to t.sub.2 PA0 (2) Period t.sub.2 to t.sub.4 PA0 (3) Time t.sub.4 PA0 [Sample-hold Circuit]
FIG. 2 shows an example of a conventional dual correlation sampling circuit. Shown in FIG. 2 are an image sensor 1, one of a plurality of photodiodes 2, a bias power supply 3, a capacitance 4, a thin-film transistor (TFT) 5, a capacitance 6, an input signal line 7, a dual correlation sampling circuit 8, a reset switch 9, an input bias power supply 10, an operational amplifier 11, a switch 12, capacitors 13 and 14, a low-pass filter 15, a resistor 16, a capacitor 17, a buffer 18, a dc regenerating capacitor 19, a switch 20, an output reference power supply 21, a buffer 22, an output terminal 23 and a driving pulse generator 24.
Each photodiode 2 of the image sensor 1 has a cathode connected to the positive terminal of the bias power supply 3, and an anode connected to the drain of the TFT 5. The photodiode 2 detects incident light. The capacitor 4 connected to the anode of the photodiode 2 represents the sum of the capacitance of the photodiode and the drain parasitic capacitance of the TFT 5. As indicated by dotted lines, the TFT 5 has small capacitances between the gate and the drain D and between the gate and the source S due to the overlap of the drain D and the source S with the gate. The capacitance 6 represents the sum of the source parasitic capacitance of the TFT 5 and the input capacitance of the dual correlation sampling circuit 8 of an IC configuration.
The switches included in the dual correlation sampling circuit 8, i.e., an IC, are analog switches. The driving pulse generator 24 generates a pulse signal for turning on and off the TFT 5 and the switches. The input bias power supply 10 is connected through the reset switch 9 to the input signal line 7. A negative feedback circuit comprising the switch 12 and the capacitor 13 is connected to the operational amplifier 11. The operational amplifier 11 functions as a buffer (gain is 10.sup.0) when the switch 12 is closed, and functions as an amplifier at a gain dependent on the capacitance ratio between the capacitors 14 and 13 when the switch 12 is opened. The negative feedback circuit is of a dual system to enable the operational amplifier 11 to carry out dual correlation sampling.
First, an input bias voltage is applied to the operational amplifier 11 of the dual correlation sampling circuit 8 for the first sampling, and then, a composite signal produced by superposing a picture signal on the input bias voltage is applied to the dual correlation sampling circuit 8 for the second sampling. The difference between the input bias voltage and the composite signal is amplified,
The reset switch 9 is closed for a fixed period with the TFT 5 turned off. Then, the capacitance 6 is charged by the input bias power supply 10 at an input bias voltage V.sub.10. The operational amplifier 11 functions as a buffer when the switch 12 is closed after opening the reset switch 9, and provides an output voltage equal to the sum of the input voltage V.sub.10 and the offset of the operational amplifier 11. The capacitor 14 of an inverting input terminal is charged to the same voltage by the negative feedback. When the offset of the operational amplifier 11 is negligibly small as compared with the input bias voltage V.sub.10, the voltage of the charged capacitor 14 is equal to the input bias voltage V.sub.10.
The output voltage V.sub.10 of the operational amplifier 11 is applied through the low-pass filter 15 and the buffer 18 to the dc regenerating capacitor 19. In this state the switch 20 is closed and the output voltage V.sub.21 of the output reference power supply 21 is applied to the dc regenerating capacitor 19 in the reverse direction. Then, dc regenerating capacitor 19 is charged at a voltage equal to (V.sub.10 -V.sub.21). Then, the switch 20 is opened.
The low-pass filter 15 reduces noise. Generally, the design cutoff frequency of an amplifier has a margin because the cutoff frequency is somewhat affected by process errors introduced into the amplifier during manufacture and the parasitic capacitance thereof. Therefore, the amplifier amplifies noise of frequencies outside a necessary frequency band. The low-pass filter 15 eliminates such noise. The buffer 18 increases impedance on the input side with respect to the low-pass filter 15, and reduces impedance on the output side with respect to the dc regenerating capacitor 19. Without the buffer 18, the dc regenerating capacitor 19 is a load on the low-pass filter 15 and may possibly lower the cutoff frequency of the low-pass filter 15 and narrow the frequency band.
The photodiode 2 produces a current approximately proportional to the total illumination and charges the capacitance 4, which generates a picture signal .DELTA.V. When the TFT 5 is turned on, the sum of the voltage V.sub.10 and the picture signal .DELTA.V is applied to the operational amplifier 11. When the gain A.sub.11 of the operational amplifier 11 is, for example, 10.sup.2, the output voltage of the operational amplifier 11 is: V.sub.10 +100 .DELTA.V. The output voltage of the operational amplifier 11 is applied through the low-pass filter 15 and the buffer 18 to the dc regenerating capacitor 19. Since the dc regenerating capacitor 19 has been charged at a voltage of (V.sub.10 -V.sub.21), the remainder of subtraction of the voltage (V.sub.10 -V.sub.21) from the voltage (V.sub.10 +100 .DELTA.V) is applied to the input terminal of the buffer 22. EQU (V.sub.10 +100 .DELTA.V)-(V.sub.10 -V.sub.21)=100 .DELTA.V+V.sub.21
Consequently, a voltage of (100 .DELTA.V+V.sub.21) appears at the output terminal 23.
FIG. 3 is a time chart of assistance in explaining the operation of the picture signal processor, in which curves of solid lines indicate the waveforms of signals in a dark state, i.e., a state where there is no incident radiant flux on the image sensor 1, and curves of long and short dash lines indicate the waveforms of signals in an illuminated state where there is some incident radiant flux on the image sensor 1.
When a TFT gate driving signal goes HIGH at time t.sub.1 as shown in (b) of FIG. 3, feed-through, i.e., leakage of a gate signal into the drain or the source, occurs and, consequently, the voltage of the capacitance 6 is increased by the leakage signal (charge) accordingly, which is represented by an increase in the input signal applied to the operational amplifier 11 to a section C-1 at time t.sub.1 in (c) of FIG. 3. Although such an increase in the input signal applied to the operational amplifier 11 in a dark state is due to only the feed-through voltage, the input signal .DELTA.V is added to the feed-through voltage and the input signal applied to the operational amplifier 11 increases to a level indicated by alternate long and short dash line in (c) of FIG. 3 in an illuminated state.
The operational amplifier 11 amplifies the input voltage including the feed-through voltage as represented by a curve in (d) of FIG. 3 and gives an amplified input voltage to the low-pass filter 15. Then, the output of the low-pass filter 15 increases at a time constant toward the output of the operational amplifier 11 as shown in (e) of FIG. 3.
When the TFT gate driving signal goes LOW at time t.sub.2 as shown in (b) of FIG. 3, the same quantity of charge as that leaked into the capacitance 6 when the TFT gate driving signal went HIGH leaks out from the capacitance 6 and, consequently, the potential of the input signal line 7 drops by a voltage corresponding to the leakage charge (feed-through voltage) and the level of the output of the operational amplifier is lowered accordingly. The output of the low-pass filter 15 decreases toward the output of the operational amplifier 11 at a time constant from the high value including the amplified feed-through voltage.
The output of the dual correlation sampling circuit 8 is transferred through the output terminal 23 (FIG. 2) to a sample-and-hold circuit, not shown, and is held by the sample-and-hold circuit. A value corresponding to an output E.sub.1 is obtained in the dark state and a value corresponding to an output E.sub.2 is obtained in the illuminated state by sampling in a time period t.sub.3 between times t.sub.2 and t.sub.4.
The input on the input signal line 7 is reset when the reset switch 9 is closed at time t.sub.4.
FIG. 8 shows a conventional dual sample-and-hold circuit. Shown in FIG. 8 are a first sample-and-hold circuit 40, a second sample-and-hold circuit 41, operational amplifiers 42, a switch 43, capacitors 44 and 44B, switches 45 and 46, switches 47, capacitors 48, switches 49 and 50, an operational amplifier 51 and an output terminal 52. The switches are analog switches, such as MOSFETs.
The inverting input terminal (-) of the operational amplifier 42 is connected through the switch 43 to the output terminal of the operational amplifier 42, and through the capacitor 44 and the switch 45 to a ground of a fixed potential(earth). The junction of the capacitor 44 and the switch 45 is connected through the switch 46 to the output terminal of the operational amplifier 42. The output terminal of the operational amplifier 42 is connected through the switch 47 to the capacitor 48 for holding samples, and the junction of the operational amplifier 42 and the capacitor 48 is connected through the switch 49 to the input terminal of the operational amplifier 51. The inverting input terminal (-) of the operational amplifier 51 is connected to the output terminal of the same for buffer action. The configuration of the second sample-and-hold circuit 41 is the same as that of the first sample-and-hold circuit 40.
The operation of the first sample-and-hold circuit 40 will be described hereinafter. The output of a dual correlation sampling circuit is applied to the input terminal 39. The switches 43 and 45 are closed and the switches 46, 47 and 49 are opened when an input bias voltage is applied to the input signal line 7 of the dual correlation sampling circuit. Then, negative feedback of 100% is made for the operational amplifier 42 and the operational amplifier 42 functions as a buffer. Suppose that the input bias voltage is V.sub.i and the offset voltage of the operational amplifier 42 is V.sub.i0. Then, a voltage equal to (V.sub.i +V.sub.i0) applied to the noninverting input terminal (+) appears at the output terminal of the operational amplifier 42 and the capacitor 44 is charged at the voltage (V.sub.i +V.sub.i0).
When the output V.sub.s of the dual correlation sampling circuit provided when a picture signal is given to the dual correlation sampling circuit is superposed on the voltage V.sub.i of the input terminal 39 with the switches 43 and 45 open, the switches 46 and 47 closed and the switch 49 open, the voltage at the input terminal 39 is equal to (V.sub.s +V.sub.i). When the operational amplifier 42 provides an output voltage V.sub.42 in this state, a voltage equal to (V.sub.42 +V.sub.i +V.sub.i0) is applied to the inverting input terminal (-). The operational amplifier 42 operates so as to meet a condition expressed by: EQU (V.sub.s +V.sub.i)-(V.sub.42 +V.sub.i +V.sub.i0)=-V.sub.i0
Therefore, V.sub.42 =V.sub.s. the capacitor 48 is charged at the input signal V.sub.s for sampling and holding when the switch 47 is closed.
The data thus held is transferred through the operational amplifier 51 to the output terminal 52 when the switch 49 is closed. While the first sample-and-hold circuit 40 is in an output operation, the second sample-and-hold circuit 41 may be operated to hold the next data.
Known picture signal processors are disclosed in, for example, Japanese Patent Laid-Open Nos. Sho 62-185458(1987) and Sho 62-135775(1987).
The prior art described above has the following problems.
First, the dual correlation sampling circuit of FIG. 2, when operating at a high operating speed, is unable to provide correct outputs.
Secondly, the dual correlation sampling circuit of FIG. 2 has a large circuit scale and consumes much power because the two buffers connected to the output of the low-pass filter are necessary.
Thirdly, when the two sample-and-hold circuits are employed in a dual arrangement and the respective voltages of the two charged capacitors 44 and 44B for cancelling the offset voltage of the operational amplifier are different from each other, the output levels differ from each other due to the difference in voltage between the two capacitors 44 and 44B in spite of same input voltage applied to both sample-and-hold circuits and the difference translates into periodic noise.
The first problem: The output E.sub.1 (E.sub.2) sampled in the time period t.sub.3, in which the output of the low-pass filter is decreasing at the time constant, is greater than a correct value to be properly sampled, i.e., a value at the termination of the decrease. Although the correct value can be sampled if the output of the low-pass filter is sampled at the termination of the decrease, such a mode of sampling reduces the operating speed.
A technique relating to the low-pass filter and the sample-and-hold circuit of apparatus relating to picture reading are proposed in Japanese Patent Laid-Open No. Hei 3-295362(1991). This technique reduces the time constant of a low-pass filter when a light source is turned on (when the apparatus is started) and increases the time constant when reading a document. Thus, the previously proposed technique is different from the present invention in the object of application.
The second problem; As shown in FIG. 2, the two buffers 18 and 22 are arranged behind the low-pass filter 15. Many circuit elements are necessary to form the two buffers 18 and 22, and the circuit elements require high power and consume much power. Since buffers deteriorate the linearity of signals and generate noise, the use of the two buffers is disadvantageous.
The third problem: The circuit shown in FIG. 8 has the two sample-and-hold circuits for one and the same image sensor, and input signals are given alternately to the two sample-and-hold circuits. The capacitors 44 and 44B are provided for cancelling the offsets of the operational amplifiers. However, these capacitors are unable to cancel the offsets perfectly due to parasitic capacitances, not shown. If voltages not cancelled by the two sample-and-hold circuits are different from each other, the difference between the voltages not cancelled affects the alternate outputs generating periodic noise.